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Description: 用VHDL编写的由FPGA控制SDRAM的存储控制程序-VHDL prepared by the FPGA control SDRAM memory control procedures
Platform: |
Size: 924 |
Author: 杨承凯 |
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Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input / Solution Series (ISERDES) and serial output / Solution Series (O Legacy) function.
Platform: |
Size: 297475 |
Author: mingming |
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Description: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Platform: |
Size: 212389 |
Author: eva |
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Description: XILINX的FPGA实现的双口ram源码，可作为dsp\\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \\ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: |
Size: 19762 |
Author: 朱效志 |
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Description: This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Platform: |
Size: 114780 |
Author: king.xia |
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Description: 在信息处理中，特别是实时视频图像处理中，通常都要对实现视频图像进行处理，而这首先必须设计大容量的存储器，同步动态随机存储器SDRAM虽然有价格低廉、容量大等优点，但因SDRAM的控制结构复杂，常用的方法是设计SDRAM通用控制器，这使得很多人不得不放弃使用SDRAM而使用价格昂贵的SRAM。为此，笔者在研究有关文献的基础上，根据具体情况提出一种独特的方法，实现了对SDRAM的控制，并通过利用FPGA控制数据存取的顺序来实现对数字视频图像的旋转，截取、平移等实时处理。
Platform: |
Size: 137424 |
Author: 赵明玺 |
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Description: verilog hdl coding DDR sdram control for fpga
Platform: |
Size: 27946 |
Author: 王郁 |
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Description: 已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度就可以了.
Platform: |
Size: 187524 |
Author: chen qiming |
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Description: 使用FPGA做SDRAM控制器
Platform: |
Size: 357433 |
Author: KAICHI |
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Description: FPGA的Nios配合时如何计算SDRAM相位的文章
Platform: |
Size: 111094 |
Author: chen |
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Description: 基于FPGA 实现DDR SDRAM的控制器
Platform: |
Size: 474402 |
Author: 张宁 |
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Description: FPGA读写SDRAM的实例，可以当作IPcore来添加，非常有价值的的程序。
Platform: |
Size: 19839930 |
Author: 陈泸华 |
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Description: verilog语言
利用FPGA控制SDRAM，相信很多朋友都需要
快下载吧
Platform: |
Size: 19766 |
Author: 杜菲 |
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Description: 该文档是作为sdram操作协议，可以作为FPGA或Asic编写代码时使用。
Platform: |
Size: 663697 |
Author: 陈泽霖 |
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Description: 基于FPGA的SDRAM设计，相信大家都会感兴趣！原版的外文书
Platform: |
Size: 6116754 |
Author: 邓振淼 |
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Description: 可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的
Platform: |
Size: 9560 |
Author: 郑宏超 |
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Description: 针对主控制板上存储器(SRAM) 存储的数据量小和最高频率低的情况,提出了基于SDR Sdram(同步动态RAM) 作为主存储器的LED 显示系统的研究。在实验中,使用了现场可编程门阵列( FPGA) 来实现各模块的逻辑功能。最终实现了对L ED 显示屏的控制,并且一块主控制板最大限度的控制了256 ×128 个像素点,基于相同条件,比静态内存控制的面积大了一倍,验证了动态内存核[7 ]的实用性。
Platform: |
Size: 511642 |
Author: 郑宏超 |
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Description: This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Platform: |
Size: 114688 |
Author: |
Hits:
Description: FPGA的Nios配合时如何计算SDRAM相位的文章-FPGA co-ordination of the Nios how to calculate the phase-SDRAM article
Platform: |
Size: 110592 |
Author: chen |
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Description: 用于控制外部sdram，是fpga连接外部sdram的桥梁，希望对大家有用(For controlling external SDRAM, it is a bridge for FPGA to connect external SDRAM. It is useful for everyone.)
Platform: |
Size: 8192 |
Author: hivickey |
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